As known and illustrated FIG. 1, a flash memory array 1 comprises a plurality of cells 2 arranged in rows and columns. The gate terminals of the cells arranged in a same row are connected to a respective word line 3, and the drain terminals of the cells belonging to a same column are to a respective bit line 4. The word lines 3 are connected to a row decoder 5, and the bit lines 4 are connected to a column decoder 6. A control unit 7 is connected with and supplies the decoders 5 and 6 with address and control signals for selecting, each time, only one word line 3 and only one bit line 4. Thereby, it is possible to access the cell 2 connected to the selected word and bit lines.
In particular, reading of a cell 2 can be done by biasing the selected word line 3 at a preset potential V.sub.cpx (for example, 6-7 V) and forcing a bias current I.sub.f in the selected bit line 4. If the selected cell is biased so that it may operate in the linear region, the value of the current I.sub.f is expressed by the following equation: EQU I.sub.f =K*(W/L)*[(V.sub.cpx -V.sub.th)*V.sub.DS -V.sup.2.sub.DS /2](1)
wherein K is a constant linked to the cell fabrication process, (W/L) is the cell dimensional width/length ratio, V.sub.th is the cell threshold voltage (i.e., the minimum potential difference to be applied between the gate and source terminals of the cell for it to start conducting current), V.sub.DS is the drain-source voltage drop of the cell, and the term (V.sub.cpx -V.sub.th) is the overdrive of the cell.
When the cell is suitably biased, the potential difference V.sub.DS is constant, and the term V.sup.2.sub.DS /2 is negligble. Consequently, in the described conditions, the current I.sub.f flowing through the cell is linearly dependent upon the threshold voltage V.sub.th.
The bit line 4 is connected with a sense amplifier having the task of detecting the current I.sub.f flowing in cell, and, in the case of analog reading, is able to supply an output signal correlated to the threshold voltage of the cell 2.
Different solutions are known for the structure of sense amplifiers for reading flash memory cells.
A first solution regards so-called direct reading amplifier circuits wherein the drain terminal of the cell to be read is connected to a load element through a bias transistor. In this case, the output of the sense amplifier is given by the potential at one terminal of the load element, normally a diode-connected MOS transistor (i.e., with gate and drain terminals short-circuited). The bias transistor limits the potential drop between the drain and source terminals of the cell to be read, so that the cell may work in the linear region, and the soft-programming phenomenon, i.e., undesired writing of the cell during the reading phase, may moreover be prevented.
Sense amplifiers of this kind are easy to manufacture but are subject to drawbacks that limit their precision. In particular, besides being affected by process variations and being sensitive to variations in temperature and supply voltage, they have reduced dynamics and poor linearity due to the presence of the diode-configuration MOS transistor.
A second solution comprises amplifier circuits with differential architecture. In this case, the current flowing in the cell to be read is compared with the current of a reference branch, which comprises a virgin flash cell identical to those of the memory array. The cell to be read and the reference cell are biased so as to present equal gate-to-source voltages and equal drain-to-source voltages. The cells are connected to respective loads through bias transistors having a topology similar to that of direct reading amplifiers. The voltages at the nodes connecting the loads to the respective cells, the difference of which depends upon the difference between the threshold voltage of the reference cell and the threshold voltage of the cell to be read, are supplied at input to an operational amplifier. The output of the latter can therefore be set with respect to the threshold voltage of the cell to be read.
This second solution reduces the dependence on the temperature and process variations, but it is not well suited to analog-type reading due to the operational amplifier operating in open loop. In addition, it has considerable overall dimensions due to the reference branch and, specifically, the reference flash cell. In fact, in order to obtain reliable performance, it is necessary to use an internal cell of a small array of flash cells, because a single cell is affected by edge effects.
A third solution is described in European Patent Application No. 97830172.9 filed on Apr. 15, 1997 in the name of ST Microelectronics, S.r.l., entitled "High-precision analog read circuit for memory arrays, in particular flash analog memory matrices", where a closed-loop circuit is described having a first branch comprising the cell to be read and a second branch comprising a reference cell. A current mirror forces equal currents in the two branches. The voltages of the drain terminals of the transistors of the current mirror are supplied to the inputs of an operational amplifier, having an output connected to the gate terminal of the reference cell. The described circuit configuration imposes that the cell to be read and the reference cell have the same overdrive voltage, so that the voltage at the output terminal of the operational amplifier (and hence at the gate terminal of the reference cell) is linearly dependent upon the threshold voltage of the cell to be read. This solution has the same drawbacks due to the presence of load transistors in diode configuration as the circuits according to the first solution and the same drawbacks due to the presence of reference cells as the circuits according to the second solution.